Spi Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

SPI Registers

The following sections describe the registers associated with the Serial
Peripheral Interface (SPI).
SPI Port Status Register (SPISTAT)
The SPI Status register (
complete or if transmission/reception errors occur. The
can be read at any time.
Some of the bits in the
cleared. The remainder of the bits can be read, but can also be cleared by a
write one-to-clear (W1C-type) operation. Bits that provide information
about the SPI are also read-only; these bits get set and cleared by the hard-
ware. Bits that are W1C-type are set when an error condition occurs (see
Table A-25 on page
cleared by software. To clear a W1C-type bit, the program must write
a one to the desired bit position of the
the bit is set, the program must write a one to bit 2 of
TUNF
clear the
TUNF
register without changing its value.

Write one-to-clear (W1C-type) bits can only be cleared by writing
1 to them. Writing zero does not clear (or have any effect on) a
W1C-type bit.
SPISTAT
A-92
) is used to detect when an SPI transfer is
SPISTAT
register are read-only (RO) and cannot be
SPISTAT
A-93); these bits are set by hardware and must be
error condition. This allows the program to read the status
Table A-25
register.
ADSP-2126x SHARC Processor Hardware Reference
register. For example, if
SPISTAT
provides the bit descriptions for the
register
SPISTAT
to
SPISTAT