Spi Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Interrupts

Transmitter packing example:
The value
0xXXLMXXJK
the data words to be transmitted out of the SPI port) is written to the
register. The processor transmits
TXSPI
Receiver packing example:
The receiver unpacks the value and two words are received,
. They appear in the
0xLM
0x00LM00JK
0xFFLMFFJK
SPI Interrupts
The SPI port can generate an interrupt in five different situations. During
core-driven transfers, an SPI interrupt is triggered in these instances:
1. When the
from the core
2. When the
core
The (Transfer Initiation and Interrupt) register determines whether
TIMOD
the interrupt is based on the
mation, refer to the
on page A-96.
10-32
(where is any random value and
XX
register as:
RXSPI
=> if is configured to 0
SGN
=> if is configured to 1 and
SGN
buffer has the capacity to accept another word
TXSPI
buffer contains a valid word to be retrieved by the
RXSPI
or
TXSPI
bit descriptions in the
TIMOD
ADSP-2126x SHARC Processor Hardware Reference
first and then transmits
0xJK
, > 7.
L J
buffer status. For more infor-
RXSPI
SPICTL
and are
JK LM
.
0xLM
and then
0xJK
register in Table