Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 803

Delayed branches. These are JUMPS and CALL/return instructions with
the delayed branches (DB) modifier. In delayed branches, no instruction
cycles are lost in the pipeline, because the DSP executes the two instruc-
tions after the branch while the pipeline fills with instructions from the
new branch.
Denormal operands. When the biased exponent is zero, smaller numbers
can only be represented by making the integer bit (and perhaps other lead-
ing bits) of the significant zero. The numbers in this range are called
denormalized (or tiny) numbers. The use of leading zeros with denormal-
ized numbers allows smaller numbers to be represented.
Direct branches. These are JUMP or CALL/return instructions that use
an absolute—not changing at runtime—address (such as a program label)
or use a PC-relative address.
Direct reads & writes. A direct access of the DSP's internal memory or
I/O processor registers by another DSP or by a host processor.
DMA (Direct Memory Accessing). The DSP's I/O processor supports
DMA of data between DSP memory and external memory, host, or
peripherals through the external, link, and serial ports. Each DMA opera-
tion transfers an entire block of data.
DMA chaining. The DSP supports chaining together multiple DMA
sequences. In chained DMA, the I/O processor loads the next Transfer
Control Block (DMA parameters) into the DMA parameter registers when
the current DMA finishes and auto-initializes the next DMA sequence.
DMA Parameter Registers. These registers function similarly to data
address generator registers, setting up a memory access process. These reg-
isters include Internal Index registers (IISPX, IISPI), Internal Modify
registers (IMSPI), Count registers (CSPx, CSPI), Chain Pointer registers
(CPSPI), External Index registers (EIPP), External Modify registers
(EMPP), and External Count registers (ECPP).
ADSP-2126x SHARC Processor Core Manual G-3