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When using an external crystal, the maximum crystal frequency cannot
exceed 25 MHz. The internal clock generator, when used in conjunction
with the
XTAL
maximum of 25 MHz external crystal frequency. For all other external
clock sources, the maximum
Table 15-3. Clock Rate Ratios After Reset (Default)
CLKCFG[1-0]
00
01
10
11
Table 15-4. PLL Multiplier and Divider Settings
PLLD[7:6]
00 (= reset)
01
10
11
Table 15-5
shows the internal core clock switching frequency across a
range of
CLKIN
frequency is constrained by the operating range of the PLL. Note that the
goal in selecting a particular clock ratio for the processor application is to
provide the highest internal frequency, given a
If an external master clock is used, it should not drive the
the processor is not powered. The clock must be driven immediately after
power-up—otherwise, internal gates stay in an undefined (hot) state and
can draw excess current. After power-up, there should be sufficient time
for the oscillator to start up, reach full amplitude, and deliver a stable
signal to the processor before the reset is released. This may take
CLKIN
15-8
pin and an external crystal, is designed to support up to a
CLKIN
Core to CLKIN Ratio
3:1, PLLD = 2, PLLM = 6
16:1, PLLD = 2, PLLM = 32
8:1, PLLD = 2, PLLM = 16
Reserved
PLL Divider Ratio
Clock Divider = 2
Clock Divider = 4
Clock Divider = 8
Clock Divider = 16
frequencies. The minimum operational range for any given
ADSP-2126x SHARC Processor Hardware Reference
frequency is 50 MHz.
PLLM[5:0]
PLL Multiplier Ratio
000000
Clock Multiplier = 64
000001
Clock Multiplier = 1
...
...
111111
Clock Multiplier = 63
CLKIN
frequency.
pin when
CLKIN
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