Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 203

Table 4-5. Pre-Modify Addressing, Modified by 6-bit Data
(No I Register Update)
DM(Data6,I7–0)=Dreg; {DAG1}
PM(Data6,I15–8)=Dreg; {DAG2}
Dreg=DM(Data6,I7–0); {DAG1}
Dreg=PM(Data6,I15–8); {DAG2}
Table 4-6. Pre-Modify Addressing, Modified by 32-bit Data
(No I Register Update)
Ureg=DM(Data32,I7–0) (LW); {DAG1}
Ureg=PM(Data32,I15–8) (LW); {DAG2}
DM(Data32,I7–0)=Ureg (LW); {DAG1}
PM(Data32,I15–8)=Ureg (LW); {DAG2}
Table 4-7. Update (Modify) I Register, Modified by M Register
Modify(I7–0,M7–0); {DAG1}
Modify(I15–8,M15–8); {DAG2}
Table 4-8. Update (Modify) I Register, Modified by 32-bit Data
Modify(I7–0,Data32); {DAG1}
Modify(I15–8,Data32); {DAG2}
Table 4-9. Bit-Reverse and Update I Register, Modified By 32-Bit Data
Bitrev(I7–0,Data32); {DAG1}
Bitrev(I15–8,Data32); {DAG2}
ADSP-2126x SHARC Processor Hardware Reference
Data Address Generators
4-25