Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 758

I/O Processor Registers
Table A-38. Group E Sources – Miscellaneous Signals (Cont'd)
Selection Code
10011 (0x13)
10100 (0x14)
10101 (0x15)
10110 (0x16)
10111 (0x17); 11000
(0x18)
11001 (0x19)
11010 (0x1A)
11011 (0x1B)
11100 (0x1C)
11101 (0x1D)
11110 (0x1E)
11111 (0x1F)
Setting the
SRU_EXT_MISCA[30]
bit. Setting the
CA_4
bit.
EXT_MISCA_5
DAI Pin Buffer Enable Registers
(SRU_PBENx, Group F)
The Pin Enable Control registers activate the drive buffer for each of the
20 DAI pins. When the pins are not enabled (driven), they can be used as
inputs. Each of the pin enables are connected, based on the 6-bit values in
A-136
Source Signal
DAI_P20_O
TIMER0_O
TIMER1_O
TIMER2_O
Reserved
PDAP_STRB_O
PCG_CLKA_O
PCG_FSA_O
PCG_CLKB_O
PCG_FSB_O
MISC_LOW_MISC_O
MISC_HIGH_MISC_O Select Logic Level High (1) as the source
bit to
SRU_EXT_MISCA[31]
ADSP-2126x SHARC Processor Hardware Reference
Description
Select DAI Pin Buffer 20 Output as the
source
Select Timer 0 Output as the source
Select Timer 1 Output as the source
Select Timer 2 Output as the source
Select PDAP Strobe Output as the source
Select Precision Clock A Output as the source
Select Precision Frame Sync A Output as the
source
Select Precision Clock B Output as the source
Select Precision Frame Sync B Output as the
source
Select Logic Level Low (0) as the source
inverts the level of the
HIGH
bit to inverts the level of the
HIGH
EXT_MS-