Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 497

Input Data Port
efficiency. The frame sync input is used to hold off latching of the next
sample (that is, ignore the clock edges). The data then flows through the
FIFO and is transferred by a dedicated DMA channel into the core's
memory as with any IDP channel. As shown in Figure 11-6, the PDAP
can accept input words up to 20 bits wide, or can accept input words that
are packed as densely as four input words up to eight bits wide.
The register also provides a reset bit that zeros any data that
IDP_PDAP_CTL
is waiting in the packing unit to be latched into the FIFO. When asserted,
the bit (bit 30 in the register) causes the
IDP_PDAP_RESET IDP_PDAP_CTL
reset circuit to strobe, then automatically clear itself. Therefore, this bit
always returns a value of zero when read. The bit (bit 26
IDP_PORT_SELECT
in the register) selects between the two sets of pins that may
IDP_PDAP_CTL
be used as the parallel input port. When is set (= 1), the
IDP_PORT_SELECT
upper 16 bits are read from the . When is
AD[15:0] IDP_PORT_SELECT
cleared (= 0), the upper 16 bits are read from . Note that the
DAI_P[20:5]
four least significant bits (LSBs) of the parallel port input are not multi-
plexed. These input bits are always read from Digital Audio Interface
(DAI) pins 4–1, as shown in Figure 11-6. The pins are always
DAI_P[4:1]
connected as bits 3 through 0. A sample PDAP program is located at the
end of this chapter. See Listing 11-2.
ADSP-2126x SHARC Processor Hardware Reference 11-7