Phase Shift - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

respectively, these outputs are activated when a low to high transition is
sensed in the external clock (

Phase Shift

Another PCG frame sync parameter provides for phase shifting with
respect to the clock of the same unit. This feature allows shifting in time
relative to clock signals. Frame sync phase shifting is often required by
peripherals that need to lead or lag a clock signal. For example, the I
protocol specifies that the frame sync should transition from high to low
one clock cycle before the beginning of a frame. Since an I
clock cycles long, delaying the frame sync by 63 cycles produces the
required framing.
The amount of phase shifting is specified as a 20-bit value in the
bit field (bits 29–20) of the
PHASE_HI
bit field (bits 29–20) of the
FSAPHASE_LO
A single 20-bit value spans these two bit fields. The upper half of the word
[19:10] is in the
register.
PCG_CTLA_1
Similarly, the phase shift for frame sync B is specified in the
and
PCG_CTLB_1

When using a clock and frame sync as a synchronous pair, the units
must be enabled in a single atomic instruction before their parame-
ters are modified. Both units must also be disabled in a single
atomic instruction.
ADSP-2126x SHARC Processor Hardware Reference
MISCA4_I
register, and the lower half [9:0] is in the
PCG_CTLA_O
registers.
Precision Clock Generator
, ).
MISCA5_I
register and in the
PCG_CTLA_O
register for unit A.
PCG_CTLA_1
2
S
2
S frame is 64
FSA-
PCG_CTLB_O
13-7