Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 694

I/O Processor Registers
SPCTL0 (0xc00)
SPCTL1 (0xc01)
SPCTL2 (0x400)
SPCTL3 (0x401)
SPCTL4 (0x800)
SPCTL5 (0x801)
DXS_A
Data Buffer Channel A Status
11=Full 10=Partially Full
00=Empty
DERR_A
Channel A Error Status (sticky)
SPTRAN=1 Transmit Underflow Status
SPTRAN=0 Receive Overflow Status
DXS_B
Data Buffer Channel B Status
11=Full, 10=Partially Full,
00=Empty
DERR_B
Channel B Error Status (sticky)
SPTRAN=1 Transmit Underflow Status,
SPTRAN=0 Receive Overflow Status
SPTRAN
SPORT Transaction
1=Active Transmit Buffers TXSPXA/TXSPXB
0=Enable Receive Buffers RXSPXA/RXSPXB
SPEN_B
SPORT Enable B
1=Enable
0=Disable
BHD
Buffer Hang Disable
1=Ignore Core Hang
0=Core Stall when TXSPx Full or RXSPx Empty
Figure A-20. SPCTLx Control Bits – for I
A-72
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
0 1 0 0 0 0 0 0
2
S and Related Modes (Upper)
FRFS
Frame on Rising Frame Sync
1=Left Channel First (default)
0=Right Channel First
LAFS
Late Frame Sync
This bit must be set to 1.
SDEN_A
DMA Channel A Enable
1=Enable
0=Disable
SCHEN_A
DMA Channel A
Chaining Enable
1=Enable
0=Disable
SDEN_B
DMA Channel B Enable
1=Enable
0=Disable
SCHEN_B
DMA Channel B
Chaining Enable
1=Enable
0=Disable
Reserved