Spi Data Transfer Operations; Core Transmit And Receive Operations; Spi Dma - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Data Transfer Operations

SPI Data Transfer Operations
The following sections provide information on the two methods the
ADSP-2126x uses to transfer data; through the core or through DMA.

Core Transmit and Receive Operations

For core-driven SPI transfers, the software has to read from or write to the
and
RXSPI TXSPI
the buffer status before reading from or writing to these registers because
the core does not hang when it attempts to read from an empty buffer or
write to a full buffer. When the core writes to a full buffer, the data that is
in that buffer is overwritten and the SPI begins transmitting the new data.
Invalid data is obtained when the core reads from an empty buffer.

For a master, when the transmit buffer becomes empty, or the
receive buffer becomes full, the SPI device stalls the SPI clock until
it reads all the data from the receive buffer or it detects that the
transmit buffer contains a piece of data.
• For a master configured with
becomes empty, the SPI device stalls the SPI clock until a piece of
data is written to the transmit buffer.
• For a master configured with
becomes full the SPI device stalls the SPI clock until all of the data
is read from the receive buffer.

SPI DMA

The SPI has a single DMA channel associated with it that can be config-
ured to support either an SPI transmit or a receive channel, but not both
simultaneously. In addition to the
four-word deep DMA FIFO the SPI port uses to improve throughput.
10-12
registers to control the transfer. It is important to check
TXSPI
ADSP-2126x SHARC Processor Hardware Reference
= 01: When the transmit buffer
TIMOD
= 00: When the receive buffer
TIMOD
and data buffers, there is a
RXSPI