Internal Data Bus Exchange - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Buses
Because the DSP's internal memory is arranged in four 16-bit wide by
96K columns, memory is addressable in widths that are multiples of col-
umns up to 64 bits:
1 column = 16-bit words
2 columns = 32-bit words
3 columns = 48- or 40-bit words
4 columns = 64-bit words
For more information on the how the DSP works with memory words, see
"Memory Organization and Word Size" on page
The PM and DM data buses are 64 bits wide. Both data buses can handle
long word (64-bit), normal word (32-bit), Extended-precision normal
word (40-bit), and short word (16-bit) data, but only the PM data bus
carries instruction words (48-bit).

Internal Data Bus Exchange

The data buses allow programs to transfer the contents of any register in
the DSP to any other register or to any internal memory location in a sin-
gle cycle. As shown in
permits data to flow between the PM and DM data buses. The
can work as one 64-bit register or as two 32-bit registers (
The alignment of
The , , and the combined
PX1 PX2
that are accessible for register-to-register or memory-to-register transfers.
The register-to-register transfers using data registers are either 40-bit
PX
transfers for the combined
shows the bit alignment and gives an example of instructions for regis-
ter-to-register transfers.
5-6
Figure 5-2, the PM Bus Exchange (
and within
PX1 PX2
registers are Universal registers (
PX
or 32-bit transfers for
PX
ADSP-2126x SHARC Processor Hardware Reference
5-12.
appears in Figure
PX
or
PX1
) register
PX
register
PX
and ).
PX1 PX2
5-2.
)
Ureg
. Figure 5-2
PX2