Designing For High Frequency Operation; Clock Specifications And Jitter - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

reduce the effect of ringing on processor input signals with fast edges,
because the amount of hysteresis that can be used on a CMOS chip is too
small to make a difference. The small amount of hysteresis allowed is due
to restrictions on the tolerance of the VIL and VIH TTL input levels
under worst-case conditions.
V
T+
V
T
V
T-
V
IL
Figure 15-4. Input Pin Hysteresis

Designing for High Frequency Operation

Because the processor can operate at very fast clock frequencies, signal
integrity and noise problems must be considered for circuit board design
and layout. The following sections discuss these topics and suggest various
techniques to use when designing and debugging processor systems.
All synchronous behavior is specified to
encouraged to clock synchronous peripherals with this same clock source
(or a different low-skew output from the same clock driver).

Clock Specifications and Jitter

The clock signal must be free of ringing and jitter. Clock jitter can easily
be introduced into a system where more than one clock frequency exists.
ADSP-2126x SHARC Processor Hardware Reference
V
IH
ENABLES VT-
System Design
V
DDEXT
ENABLES VT+
. System designers are
CLKIN
GND
15-15