Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 768

I/O Processor Registers
Table A-43. PCG_CTLB_1 Register Bit Descriptions
Bits Name
19–0 CLKBDIV
29–20 FSBPHASE_LO
30 FSBSOURCE
31 CLKBSOURCE
PCG_PW (0x24C4)
Reserved
INVFSB
Active Low Frame Sync B
Reserved
INVFSA
Active Low Frame Sync A
Figure A-60. PCG_PW Register (Bypass Mode)
A-146
Description
Divisor for Clock B.
Phase for Frame Sync B. Note: This field represents the
lower half of the 20-bit value for the channel B frame sync
phase. The phase represents the number of input clocks
remaining in the first frame after the signal is enabled.
See also FSBPHASE_HI (Bits 29-20) in PCG_CTLB_0
shown in
Frame Sync B Source. Master Clock Source for Frame
Sync B.
0 = CLKIN input selected for Frame Sync B
1 = PCG_EXTB_I selected for Frame Sync B
Clock B Source. Master Clock Source for Clock B.
0 = CLKIN input selected for Clock B
1 = PCG_EXTB_I selected for Clock B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
Figure A-58 on page A-144.
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
STROBEB
One Shot Frame Sync B
STROBEA
One Shot Frame Sync A