Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 198

DAGs, Registers, and Memory
63
0X0000 0000
Figure 4-5. Normal Word (32-bit) DAG Register Memory Transfers
The DAGs align extended-precision normal word (40-bit) addressed
transfers or register-to-register transfers to bits 39-8 of the buses. These
transfers between a 40-bit data register and 32-bit DAG1 or DAG2 regis-
ters use the 64-bit DM and PM data buses.
transfers.
63
0X0000 00
Figure 4-6. DAG Register-to-Data Register Transfers
Long word (64-bit) addressed transfers between memory and 32-bit
DAG1 or DAG2 registers target double DAG registers and use the 64-bit
DM and PM data buses.
transfers.
If the long word transfer specifies an even numbered DAG register (
), then the even numbered register value transfers on the lower half of
I2
the 64-bit bus, and the even numbered register + 1 value transfers on the
upper half (bits 63-32) of the bus.
If the long word transfer specifies an odd numbered DAG register (
), the odd numbered register value transfers on the lower half of the
B3
4-20
DM OR PM DATA BUS
31
31
DAG1 OR DAG2 REGISTERS
DM OR PM DATA BUS
39
39
DAG1 OR DAG2 REGISTERS
Figure 4-7 illustrates how the bus works in these
ADSP-2126x SHARC Processor Hardware Reference
Figure 4-6 illustrates these
8
0X00
0
0
0
0
or
I0
or
I1