Jtag Test Emulation Port; Jtag Test Access Port - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

6 JTAG TEST EMULATION PORT

In addition to boundary scan, the JTAG Test Emulation Port supports
other functions including background telemetry channels, cycle counting
with , user-configurable hardware support, breakpoints, and a reg-
EMUCLK
ister for viewing the revision ID.

JTAG Test Access Port

The emulator uses JTAG boundary scan logic for ADSP-2126x communi-
cations and control. This JTAG logic consists of a state machine, a five
pin Test Access Port (TAP), and Shift registers. The state machine and
pins conform to the IEEE 1149.1 specification. The TAP pins appear in
Table 6-1. A special pin (
Devices. This pin is not defined in the IEEE-1149.1 specification. This
signal notifies the JTAG ICE that the processor has completed an
operation.
Table 6-1. JTAG Test Access Port (TAP) Pins
Pin I/O
TCK I
TMS I
TDI I
TDO O
I
TRST
1 Asynchronous with CLKIN
ADSP-2126x SHARC Processor Hardware Reference
) is used in the JTAG emulators from Analog
EMU
Function
Test Clock: pin used to clock the TAP state machine
Test Mode Select: pin used to control the TAP state machine sequence
Test Data In: serial shift data input pin
Test Data Out: serial shift data output pin
Test Logic Reset: resets the TAP state machine
1
6-1