Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 142

Loops and Sequencing
Table 3-12. Pipelined Execution Cycles for Two Instruction Counterbased
Loop with Two Iterations
Cycles 1
Execute 1
N
Decode N + 1
Fetch N + 2
N is the loop start instruction and N + 3 is the instruction after the loop.
1. Loop count (LCNTR) equals 2
2. PC Stack supplies loop start address
3. Count expired tests true
4. Loop iteration aborts; PC and loop stacks pop
Table 3-13. Pipelined Execution Cycles for Two Instruction Counterbased
Loop with One Iteration (Two Overhead Cycles)
Cycles 1
Execute 1
N
Decode N + 1
Fetch N + 2
N is the loop start instruction and N + 3 is the instruction after the loop.
1. Loop count (LCNTR) equals 1
2. PC Stack supplies loop start address
3. Count expired tests true
4. Loop iteration aborts; PC and loop stacks pop; N + 1 suppressed
5. N + 2 suppressed
Processing of an interrupt that occurs during the last iteration of a one
instruction loop is delayed by one cycle when:
• the loop executes once or twice,
• a two instruction loop executes once, or
• a cycle follows one of these loops.
NOP
3-30
2 3
N + 1 (Pass 1) N + 2 (Pass 1) N + 1 (Pass 2) N + 2 (Pass 2) N + 3
N + 21 N + 1
2 3
N + 1 N + 2
2 3
N + 1 (Pass 1) N + 1 (Pass 1) NOP
N + 2 N + 1 –>
4
NOP
2 3
N + 1 N + 2
ADSP-2126x SHARC Processor Hardware Reference
4 5
N + 2 N + 3
N + 4
4
N + 3
4 5
NOP
N + 2 –> N + 3
5
NOP
N + 3 N + 4
6
N + 4
N + 5
6
N + 3
N + 4
N + 5