Processor Core; Processing Elements - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The following sections summarize the features of each functional block in
the ADSP-2126x architecture.

Processor Core

The processor core of the ADSP-2126x consists of two processing ele-
ments (each with three computation units and data register file), a
program sequencer, two data address generators, a timer, and an instruc-
tion cache. All digital signal processing occurs in the processor core.

Processing Elements

The processor core contains two processing elements: PEx and PEy. Each
element contains a data register file and three independent computation
units: an arithmetic logic unit (ALU), a multiplier with an 80-bit
fixed-point accumulator, and a shifter. For meeting a wide variety of pro-
cessing needs, the computation units process data in three formats: 32-bit
fixed-point, 32-bit floating-point, and 40-bit floating-point. The float-
ing-point operations are single-precision IEEE-compatible. The 32-bit
floating-point format is the standard IEEE format, whereas the 40-bit
extended-precision format has eight additional Least Significant Bits
(LSBs) of mantissa for greater accuracy.
The ALU performs a set of arithmetic and logic operations on both
fixed-point and floating-point formats. The multiplier performs float-
ing-point or fixed-point multiplication and fixed-point
multiply/accumulate or multiply/cumulative-subtract operations. The
shifter performs logical and arithmetic shifts, bit manipulation, bit-wise
field deposit and extraction, and exponent derivation operations on 32-bit
operands. These computation units complete all operations in a single
cycle; there is no computation pipeline. The output of any unit may serve
as the input of any unit on the next cycle. All units are connected in paral-
lel, rather than serially. In a multifunction computation, the ALU and
multiplier perform independent, simultaneous operations.
ADSP-2126x SHARC Processor Hardware Reference
Introduction
1-5