Arithmetic Status Registers (Astatx And Astaty) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Arithmetic Status Registers (ASTATx and ASTATy)

The and
ASTATx
tem registers (
Ureg
register. The
ASTATx
register indicates status for PEy operations.
ASTATy
Table A-4 provide bit information for the
CACC (31–24)
Compare Accumulation Shift Bits
SF
Shifter Bit FIFO
SS
Shifter Input Sign
SZ
Shifter Zero
SV
Shifter Overflow
AF
ALU Floating-Point Operation
MI
Multiplier Floating-Point Invalid Operation
MU
Multiplier Floating-Point Underflow
MV
Multiplier Overflow
Figure A-4. ASTAT Register

If these registers are loaded manually, there is a one cycle effect
latency before the new value in the
conditional instruction.
ADSP-2126x SHARC Processor Hardware Reference
registers are non memory-mapped, universal, sys-
ASTATy
and ). Each processing element has its own
Sreg
register indicates status for PEx operations, the
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9
0 0 0 0 0 0 0
Registers Reference
Figure A-4
registers.
ASTAT
0 0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
register can be used in a
ASTATx
ASTAT
and
0
BTF
Bit Test Flag for System
Registers
0
0
AZ
ALU Zero/Float-
ing-Point Underflow
AV
ALU Overflow
AN
ALU Negative
AC
ALU Fixed-Point Carry
AS
ALU X-Input Sign
(for ABS and MANT)
AI
ALU Floating-Point
Invalid Operation
MN
Multiplier Negative
A-11