Reset Generators - Analog Devices ADSP-21261 SHARC Hardware Reference Manual


100 s depending on the choice of crystal, operating frequency, loop gain
and capacitor ratios. For details on timing, refer to the product-specific
data sheet.
After the external processor
ating. The rest of the chip will be held in reset for 4096
is deasserted by an internal reset signal. This sequence allows the
RESET
PLL to lock and stabilize. Add one
requirements with respect to the
Table 15-5. Selecting Core to CLKIN Ratio
Typical Crystal and Clock Oscillators Inputs
12.5
Clock Ratios Core CLK (MHz)
3:1 37.5
8:1 100
16:1 200

Reset Generators

It is important that a processor (or programmable device) have a reliable
active that is released once the power supplies and internal clock cir-
RESET
cuits have stabilized. The
delay, but it should also have a clean monotonic edge. Analog Devices has
a range of microprocessor supervisory ICs with different features. Features
include one or more of the following:
• Power-up reset
• Optional manual reset input
ADSP-2126x SHARC Processor Hardware Reference
signal is deasserted, the PLL starts oper-
RESET
CLKIN
falling edge.
CLKIN
16.67 25 33.3
50 75 100
133.36 200 N/A
N/A N/A N/A
signal should not only offer a suitable
RESET
System Design
CLKIN
cycle if doesn't meet setup
RESET
40 50
120 150
N/A N/A
N/A N/A
cycles after
15-9