Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 740

I/O Processor Registers
Table A-34. Group A Sources – Serial Clock (Cont'd)
Selection Code
11010 (0x1A)
11011 (0x1B)
11100 (0x1C)
11101 (0x1D)
11110 (0x1E)
11111 (0x1F)
Setting
SRU_CLK3[4:0]
.
PCG_CLKA_O
Setting
SRU_CLK3[9:5]
.
PCG_CLKB_0
Serial Data Routing Registers
(SRU_DATx, Group B)
The Serial Data Routing Control registers route serial data to the serial
ports (a, b) and the IDP. Each of the data inputs specified are connected
to a data source based on the six bit values shown in
Sixty-four possible data sources can be designated for these registers:
•
SRU_DAT0
•
SRU_DAT1
•
SRU_DAT2
•
SRU_DAT3
•
SRU_DAT4
A-118
Source Signal
Reserved
Reserved
PCG_CLKA_O
PCG_CLKB_O
LOW
HIGH
= 28 connects
= 29 connects
, described in Figure A-38
, described in Figure A-39
, described in Figure A-40
, described in Figure A-41
, described in Figure A-42
ADSP-2126x SHARC Processor Hardware Reference
Description
Select Precision Clock A Output as the source
Select Precision Clock B Output as the source
Select Logic Level Low (0) as the source
Select Logic Level High (1) as the source
to logic low, not to
PCG_EXTA_I
to logic low, not to
PCG_EXTB_I
Table A-35.