Eemuout Register; Emulation Clock Counter Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table A-20. EEMUSTAT Register Bit Descriptions (Cont'd)
Bit Name
13 EEMUENS
14 Reserved
15 EEMUINENS
16 STATIO1
31–17 Reserved
1 Internal hardware sets this bit.
2 This bit is set and reset by the core.
3 The FIFO controller sets and resets this bit.
4 Internal hardware sets and resets this bit.

EEMUOUT Register

The register is a four-deep memory, 32-bit memory-mapped I/O
EEMUOUT
buffer that is writable by the core. Its address is 0x30022.

Emulation Clock Counter Registers

The (clock counter) and
EMUCLK
are located in the Universal (
ters are user accessible and can be written only when the DSP is in
emulation space. These registers are read-only from normal-space and can
be written only when the ADSP-2126x is in emulation space. The Emula-
tion Clock Counter consists of a 32-bit Count register (
32-bit scaling register (
ADSP-2126x SHARC Processor Hardware Reference
Description
Enhanced Emulation Feature Enable.
0 = Enhanced emulation feature enable
1 = Enhanced emulation feature disable
EEMUIN Interrupt Enable.
0 = EEMUIN interrupt disable
1 = EEMUIN interrupt enable
DMA EP Address Breakpoint Status. Set bit if breakpoint
hit detected on the IOD1 bus (between EP and internal
memory)
0 = No EP DMA breakpoint occurs
1 = EP DMA Breakpoint occurs
(reserved for ADSP-21362/3/4/5/6 processors)
EMUCLK2
) register set.
Ureg
). The
EMUCLK2 EMUCLK
Registers Reference
4
4
(clock counter scaling) registers
and
EMUCLK EMUCLK2
EMUCLK
register counts clock cycles
regis-
) and a
A-61