Dai System Design - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

DAI System Design

This virtual connectivity design offers a number of distinct advantages:
• Flexibility
• Increased numbers and kinds of configurations
• Connections can be made via software—no hard-wiring is required

Inputs may only be connected to outputs.
DAI System Design
Figure and Figure
SRU. The SRU allows for very flexible data routing. In its design, the DAI
makes use of several types of data from a large variety of sources,
including:
• Timers, which are shown in
• Six serial ports (SPORTS). Serial ports offer Left-justified Sample
Pair and I
receive or transmit pins. These pins support up to 24 transmit or
24 receive I
or six full-duplex TDM streams of up to 128 channels per frame.
For more information, see "Serial Ports" on page 9-1.
• Precision Clock Generators (PCG). The PCG consists of two units,
each of which generates a pair of signals derived from a clock input
signal. See
information.
• Input Data Port (IDP). The IDP provides an additional mecha-
nism for peripherals to communicate with memory. Part of the
IDP's function is to convert information from serial format to par-
allel format so that it can be moved into memory using a parallel
FIFO. IDP is described in
12-2
show how the DAI pin buffers are connected via the
2
S mode support via 12 programmable and simultaneous
2
S channels of audio when all six SPORTs are enabled,
"Precision Clock Generator" on page 13-1
"Input Data Port" on page
ADSP-2126x SHARC Processor Hardware Reference
Figure .
for more
11-1.