Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 312

Setting Up DMA Parameter Registers
Similarly, DMA transfers between internal memory and serial, IDP or SPI
ports have DMA parameters. When the I/O processor performs DMA
between internal memory and one of these ports, the program sets up the
parameters, and the I/O uses the port instead of the external bus.
The direction (receive or transmit) of the I/O port determines the direc-
tion of data transfer. When the port receives data, the I/O processor
automatically transfers the data to internal memory. When the port needs
to transmit a word, the I/O processor automatically fetches the data from
internal memory.
channel data paths.
related ports, and buses.
I/O PROCESSOR
REGISTERS
(CORE DOMAIN)
Figure 7-3. I/O Processor Block Diagram
7-22
Figure 7-4 on page 7-27
Figure 7-3 shows the processor's I/O processor,
DMD, PMD BUSES
(64-BIT, TO CORE)
DMA BUS ARBITRATION / IOP MUX
I/O PROCESSOR
REGISTERS
(IOP DOMAIN)
SPI
SPI PORT
DMA
FIFOS
FIFO
(1 DEEP)
(4 DEEP)
PARALLEL
PORT FIFOS
(2 DEEP)
I/O PROCESSOR
ADSP-2126x SHARC Processor Hardware Reference
shows more detail on DMA
IOD BUS
32-BIT
SPORT
FIFOS
(2 DEEP)
IDP FIFO
(8 DEEP)