Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 356

Serial Port Signals
Any 20 of these 24 signals can be mapped to Digital Audio Interface
( ) pins through the signal routing unit (SRU).
DAI_Px
tion, see "Digital Audio Interface" in Chapter 12, Digital Audio
Interface., Table A-34 on page
A serial port receives serial data on one of its bidirectional serial data sig-
nals configured as inputs, or transmits serial data on the bidirectional
serial data signals configured as outputs. It can receive or transmit on both
channels simultaneously and unidirectionally, where the pair of data sig-
nals can both be configured as either transmitters or receivers.

The
SPORTx_DA
SPORT cannot transmit and receive data simultaneously for
full-duplex operation. Two SPORTs must be combined to achieve
full-duplex operation. The
trols the direction for both the A and B channel signals. Therefore,
the direction of channel A and channel B on a particular SPORT
must be the same.
Serial communications are synchronized to a clock signal. Every data bit
must be accompanied by a clock pulse. Each serial port can generate or
receive its own clock signal (
frequencies are configured in the
signals shift data based on the rate of
page 9-63 for more details.
In addition to the serial clock signal, data may be signaled by a frame syn-
chronization signal. The framing signal can occur at the beginning of an
individual word or at the beginning of a block of words. The configura-
tion of frame sync signals depends upon the type of serial device
connected to the processor. Each serial port can generate or receive its own
frame sync signal (
nally-generated frame sync frequencies are configured in the
registers. Both the A and B channel data signals shift data based on their
corresponding
details.
9-6
A-117, and
and
SPORTx_DB
SPORTx_CLK
) for transmitting or receiving data. Inter-
SPORTx_FS
signal. See
SPORTx_FS
ADSP-2126x SHARC Processor Hardware Reference
Table A-35 on page
channel data signals on each
bit in the
SPTRAN
). Internally-generated serial clock
registers. The A and B channel data
DIVx
. See
SPORTx_CLK
Figure 9-8 on page 9-63
For more informa-
A-121.
register con-
SPCTLx
Figure 9-8 on
DIVx
for more