I/O Processor Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

while the user has control of the DSP and stops counting when the emula-
tor gains control. These registers let you gauge the amount of time spent
executing a particular section of code. The
time can count by incrementing each time the
EMUCLK
over to zero. The combined emulation clock counter can count accurately
for thousands of hours.
I/O Processor Registers
The I/O Processor (IOP) registers are accessible as part of the processor's
memory map.
registers and provides a cross-reference to a description of each register.
These registers occupy addresses 0x0000 0000 through 0x0003 FFFF of
the memory map. The IOP memory-mapped space is sub divided into
peripheral and core memory mapped registers. The IOP registers control
the following operations: Parallel port, Serial port, Serial Peripheral Inter-
face port (SPI), and Input Data port (IDP).

IOP registers have a one cycle effect latency (changes take effect on
the second cycle after the change).
Since the IOP registers are part of the processor's memory map, buses
access these registers as locations in memory. While these registers act as
memory-mapped locations, they are separate from the processor's internal
memory and have different bus access. One bus can access one IOP regis-
ter group at a time.
When there is contention among the buses for access to registers, the pro-
cessor arbitrates register access as:
• Data Memory (DM) bus accesses
• Program Memory (PM) bus accesses
• IOP (IO) bus (lowest priority) accesses
A-62
Table A-21 on page A-63
Table A-21 on page A-63
ADSP-2126x SHARC Processor Hardware Reference
register extends the
EMUCLK2
EMUCLK
lists the IOP memory-mapped
lists the IOP register groups.
value rolls