Spi Receive Buffer Register (Rxspi) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Receive Data Buffer Shadow Register
(RXSPI_SHADOW)
Use the
RXSPI_SHADOW
software. The
RXSPI_SHADOW
, but its contents are identical to the
RXSPI
the software, the
= 00). No such hardware action occurs when the shadow register is
TIMOD
read. The
RXSPI_SHADOW
only by the software and not the DMA.
Receive Buffer Register (RXSPI)" on page A-101.

SPI Receive Buffer Register (RXSPI)

The SPI Receive Buffer register's address is 0x1004. The reset value for
this register is undefined. This is a 32-bit read-only register accessible by
the core or DMA controller. At the end of a data transfer, the
ter is loaded with the data in the Shift register. During a DMA receive
operation, the data in
memory. For core- or interrupt-driven transfers, programs can also use the
status bits in the
RXS
full.
SPI Transmit Data Buffer Register (TXSPI)
The SPI Transmit Buffer register's address is 0x1003.The reset value for
this register is undefined. This SPI Transmit Data register is a 32-bit reg-
ister which is part of the IOP register set and can be accessed by the core
or the DMA controller. Data is loaded into this register before being
transmitted. Prior to the beginning of a data transfer, data in the
register is automatically loaded into the Transmit Shift register. During a
DMA transmit operation, the data in the
loaded from internal memory.
ADSP-2126x SHARC Processor Hardware Reference
register for the receive data buffer (
register resides at a different address from
bit clears and an SPI transfer may be initiated (if
RXS
register is a read-only (RO) register accessible
is automatically loaded into the internal
RXSPI
register to determine if the receive buffer is
SPISTAT
Registers Reference
RXSPI
. When
RXSPI RXSPI
For more information, see "SPI
register is automatically
TXSPI
) to debug
is read via
regis-
RXSPI
TXSPI
A-101