Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 27

SPORT DMA Count Registers (CSPx) ............................. A-91
SPORT Chain Pointer Registers (CPSPxx) ........................ A-91
SPI Registers ........................................................................ A-92
SPI Port Status Register (SPISTAT) .................................. A-92
SPI Port Flags Register (SPIFLG) ..................................... A-95
SPI Control Register (SPICTL) ........................................ A-96
Shift Registers ................................................................ A-100
Receive Shift Register (RXSR) .................................... A-100
Transmit Shift Register (TXSR) .................................. A-100
SPI Receive Data Buffer Shadow Register
(RXSPI_SHADOW) ............................................... A-101
SPI Receive Buffer Register (RXSPI) ........................... A-101
SPI Transmit Data Buffer Register (TXSPI) .................... A-101
SPI Baud Rate Register (SPIBAUD) ............................... A-102
SPI DMA Registers ............................................................ A-103
SPI DMA Configuration (SPIDMAC) Register ............... A-103
SPI DMA Start Address Register (IISPI) ........................ A-106
SPI DMA Address Modifier Register (IMSPI) ................ A-106
SPI DMA Word Count Register (CSPI) .......................... A-107
SPI DMA Chain Pointer Register (CPSPI) ...................... A-107
Parallel Port Registers ......................................................... A-108
Parallel Port Control Register (PPCTL) .......................... A-109
Parallel Port DMA Transmit Register (TXPP) ................. A-111
Parallel Port DMA Receive Register (RXPP) ................... A-112
ADSP-2126x SHARC Processor Hardware Reference
Contents
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