Setting The Internal Serial Clock And Frame Sync Rates; Left-Justified Sample Pair Mode Control Bits; Setting Word Length (Slen) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Each SPORT transmit or receive channel has a buffer enable, DMA
enable, and chaining enable bits in its
signal is used as the transmit and/or receive word select signal.
SPORTx_FS
DMA-driven or interrupt-driven data transfers can also be selected using
bits in the
SPCTLx

Setting the Internal Serial Clock and Frame Sync Rates

The serial clock rate (
bit field in the

Left-Justified Sample Pair Mode Control Bits

Several bits in the
ple Pair mode operation:
• Operation mode (
• Channel enable (
• Word length (
• Frame on Rising Frame Sync (
• Master mode enable (
• Late Frame Sync (
For more information, see "Serial Port Registers" on page A-69.

Setting Word Length (SLEN)

SPORTs handle data words containing 8 to 32 bits in Left-justified mode.
Programs need to set the bit length for transmitting and receiving data
words. For details, see
The transmitter sends the MSB of the next word in the same clock cycle as
the word select (
ADSP-2126x SHARC Processor Hardware Reference
register.
value) for internal clocks can be set using a
CLKDIV
register. For details, see
CLKDIV
register enable and configure Left-justified Sam-
SPCTLx
)
OPMODE
and
SPEN_A
)
SLEN
MSTR
)
LAFS
"Word Length" on page 9-39
) signal changes.
SPORTx_FS
Control register. The
SPCTLx
Figure 9-8 on page
)
SPEN_B
)
FRFS
)
Serial Ports
9-63.
9-15