Short Word Addressing Of Single-Data In Simd Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings
Short Word Addressing of Single-Data in SIMD
Mode
Figure 5-13 shows the SIMD, single-data, short word addressed access
mode. For short word addressing, the processor treats the data buses as
four 16-bit short word lanes. The explicitly addressed (named in the
instruction) 16-bit value is transferred using the least significant short
word lane of the PM or DM data bus. The implicitly addressed (not
named in the instruction, but inferred from the address in SIMD mode)
short word value is transferred using the 47–32 bit short word lane of the
PM or DM data bus. The processor drives the other short word lanes of
the PM or DM data buses with zeros (31–16 bit lane and 63–48 bit lane).
The instruction explicitly accesses the register
that register's complementary register,
ister with an
RX
explicit target, the processor uses that register's complement
implicit target. For more information on complementary registers, see
"Secondary Processor Element (PEy)" on page
Figure 5-13 shows the data path for one transfer. The processor accesses
short words sequentially in memory. For more information on arranging
data in memory to take advantage of this access pattern, see
on page 5-75.
5-36
mnemonic. If the syntax named the
ADSP-2126x SHARC Processor Hardware Reference
and implicitly accesses
RX
. This instruction uses a
SX
register
PEy
5-19.
reg-
PEx
as the
SX
as the
RX
Figure 5-39