Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 721

Table A-27. SPICTL Register Bit Descriptions (Cont'd)
Bits Name
11 CLKPL
12 SPIMS
13 OPD
14 SPIEN
15 PACKEN
16 SGN
17 SMLS
18 TXFLSH
19 RXFLSH
31–20 Reserved
ADSP-2126x SHARC Processor Hardware Reference
Definition
Clock Polarity.
0 = Active-high SPICLK (SPICLK low is the idle state)
1 = Active-low SPICLK (SPICLK high is the idle state)
Master Select. Configures SPI module as master or slave
0 = Device is a slave device
1 = Device is a master device
Open Drain Output Enable. Enables open drain data output
enable (for MOSI and MISO)
0 = Normal
1 = Open Drain
SPI Port Enable.
0 = SPI Module is disabled
1 = SPI Module is enabled
Packing Enable.
0 = No Packing
1 = 8-16 Packing
Note: This bit may be 1 only when WL = 00 (8-bit transfer).
When in transmit mode, PACKEN bit will unpack data.
Sign Extend Bit.
0 = No sign extension
1 = Sign Extension
Seamless Transfer Bit.
0 = Seamless transfer disabled
1 = Seamless transfer enabled not supported in mode
TIMOD[1:0] = 00 and CPHASE = 0 for all modes.
Flush Transmit Buffer. Write a 1 to this bit to clear TXSPI
0 = TXSPI not Cleared
1 = TXSPI Cleared
Clear RXSPI. Write a 1 to this bit to clear RXSPI
0 = RXSPI not Cleared
1 = RXSPI Cleared
Registers Reference
A-99