Alternate (Secondary) Data Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Alternate (Secondary) Data Registers

• through
S0
tions, whether the DSP is in SISD or SIMD mode.
For more information on SISD and SIMD computational operations, see
"Secondary Processing Element (PEy)" on page
tion on ADSP-2126x assembly language, see SHARC Processor
Programming Reference.
Alternate (Secondary) Data Registers
Each register file has an alternate register set. To facilitate fast context
switching, the DSP includes alternate register sets for data, results, and
data address generator registers. Bits in the
alternate registers become accessible. While inaccessible, the contents of
alternate registers are not effected by DSP operations. Note that there is a
maximum one cycle latency from the time when writes are made to
and the point when an alternate register set can be accessed. The alternate
register sets for data and results are described in this section. For more
information on alternate data address generator registers, see DAG
nate (Secondary) DAG Registers" on page
Bits in the
MODE1
sets: the lower half (
- ). To share data between contexts, a program places the data to be
S8 S15
shared in one half of either the current processing element's register file or
the opposite processing element's register file and activates the alternate
register set of the other half. For information on how to activate alternate
data registers, see the description of the
Each multiplier has a primary or foreground (
background (
MRB
result register receives the result from the multiplier operation, swapping
which register is the current
switching. Unlike other registers that have alternates, both
accessible at the same time. All fixed-point multiplies can accumulate
2-40
always refer to PEy registers for data move instruc-
S15
register can activate independent alternate data register
- and -
R0 R7 S0 S7
) results register. A bit in the
or
MRF
ADSP-2126x SHARC Processor Hardware Reference
2-45. For more informa-
register control when
MODE1
4-6.
) and the upper half (
register below.
MODE1
) register and alternate or
MRF
register selects which
MODE1
. This swapping facilitates context
MRB
MODE1
"Alter-
- and
R8 R15
and are
MRF MRB