Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 236

Internal Memory Access Listings
data bus. The processor drives the other short word lanes of the data buses
with zeros.
In SISD mode, the instruction accesses the
from memory. This instruction accesses
address has "00" for its least significant two bits of address. Other loca-
tions within this row have addresses with least significant two bits of "01",
"10", or "11" and select
respectively. The syntax targets register
5-32
,
WORD X1 WORD X2
ADSP-2126x SHARC Processor Hardware Reference
registers to transfer data
PEx
, whose short word
WORD X0
, or from memory
WORD X3
in .
RX PEx