Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 174

Summary
STKYX
CORE
TIMER
TMREXP
INTERRUPTS
INTERRUPT
CONTROLLER
INTERRUPT LATCH
(IRPTL)
INTERRUPT MASK
(IMASK)
INTERRUPT MASK
POINTER (IMASKP)
INTERRUPT RETURN ADDRESS
VECTOR
32
DM DATA BUS
Figure 3-6. Program Sequencer Block Diagram
3-62
ASTATX ASTATY
INPUT
FLAGS
CONDITION
LOGIC
BRANCH
CONTROL
OTHER
PROGRAM
COUNTER STACK
TOP OF PC
STACK (PCSTK)
PC STACK
POINTER (PCSTKP)
REPEATED
ADDRESS
OR TOP OF LOOP
(IDLE)
NEXT ADDRESS MULTIPLEXER
PM ADDRESS BUS
ADSP-2126x SHARC Processor Hardware Reference
MODE1 MODE2
LOOP ADDRESS
STACK
(LADDR)
LOOP COUNT STACK
(CURLCNTR, LCNTR)
LOOP CONTROL
INSTRUCTION PIPELINE
FETCH DECODE
PROGRAM
ADDRESS ADDRESS
COUNTER
(FADDR) (DADDR)
PC-RELATIVE
ADDRESS
+1
NEXT
ADDRESS
DIRECT
(LINEAR
BRANCH
FLOW)
32
STKYY MMASK
INSTRUCTION
CACHE
INSTRUCTION
LATCH
ADDRESS
FROM DAG2
(PC)
+
INDIRECT
BRANCH
48
PM DATA BUS