I/O Processor Registers
Table A-48. IDP_PDAP_CTL Register (Cont'd)
Bits
Name
11
IDP_P12_PDAPMASK
12
IDP_P13_PDAPMASK
13
IDP_P14_PDAPMASK
14
IDP_P15_PDAPMASK
15
IDP_P16_PDAPMASK
16
IDP_P17_PDAPMASK
17
IDP_P18_PDAPMASK
18
IDP_P19_PDAPMASK
19
IDP_P20_PDAPMASK
25–20
Reserved
26
IDP_PORT_SELECT
A-156
Description
Parallel Data Acquisition Port Mask
0 = Input data from DAI_12/DATA7 is masked
1 = Input data from DAI_12/DATA7 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_13/ADDR0 is masked
1 = Input data from DAI_13/ADDR0 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_14/ADDR1 is masked
1 = Input data from DAI_14/ADDR1 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_15/ADDR2 is masked
1 = Input data from DAI_15/ADDR2 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_16/ADDR3 is masked
1 = Input data from DAI_16/ADDR3 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_17/ADDR4 is masked
1 = Input data from DAI_17/ADDR4 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_18/ADDR5 is masked
1 = Input data from DAI_18/ADDR5 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_19/ADDR6 is masked
1 = Input data from DAI_19/ADDR6 is un-masked
Parallel Data Acquisition Port Mask
0 = Input data from DAI_20/ADDR7 is masked
1 = Input data from DAI_20/ADDR7 is un-masked
Port Select: Input Pins Select
1 = Selects upper 16 inputs from AD[15:0]
(ADDR7–ADDR0, DATA7–DATA0)
0 = Selects upper 16 inputs from DAI_P[20:5]
ADSP-2126x SHARC Processor Hardware Reference
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