Interrupt Mask Pointer Register (Imaskp) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Registers

Interrupt Mask Pointer Register (IMASKP)

The register is a non-memory-mapped, universal, system register
IMASKP
( and
Ureg Sreg
the same name in the
tions are shown in
indicate user programmable interrupts.
This register supports an interrupt nesting scheme that lets higher priority
events interrupt an ISR and keeps lower priority events from interrupting.
When interrupt nesting is enabled, the bits in the
interrupts that have a lower priority than the interrupt that is currently
being serviced. Other bits in this register unmask interrupts having higher
priority than the interrupt that is currently being serviced. Interrupt nest-
ing is enabled using
a lower priority interrupt even when masked, and the processor responds
to that latched interrupt if it is later unmasked.
When interrupt nesting is disabled (
bits in the
IMASKP
rently being serviced. The
when masked, and the processor responds to the highest priority latched
interrupt after servicing the current interrupt.
A-26
). Each bit in the
IMASKP
registers. The
IRPTL
Figure A-8, and described in
in the
NESTM MODE1
register mask all interrupts while an interrupt is cur-
register still latches these interrupts even
IRPTL
ADSP-2126x SHARC Processor Hardware Reference
register corresponds to a bit with
register field descrip-
IMASKP
Table
IMASKP
register. The
IRPTL
= 0 in the
NESTM MODE1
A-9. Shaded cells
register mask
register latches
register), the