Spi Word Lengths - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The bit defines when the receive buffer can be read; the
RXS
when the transmit buffer can be filled. The end of a single word transfer
occurs when the
received and latched into the receive buffer,
shortly after the last sampling edge of
few core clock cycles and is independent of
rate. If configured to generate an interrupt when
00), the interrupt becomes active one core clock cycle after
When not relying on this interrupt, the end of a transfer can be detected
by polling the
To maintain software compatibility with other SPI devices, the SPI Trans-
fer Finished bit (
slightly different behavior from that of other commercially available
devices. For a slave device,
device, is set one-half of the
SPIF
regardless of
CPHASE
The baud rate determines when the
after , but at the lowest baud rate settings (
RXS
set before the
RXS
latched into the
sor must wait for the
buffer. For larger
RXSPI
is set.
SPIF

SPI Word Lengths

The processor's SPI port can transmit and receive the word widths
described in the following sections.
ADSP-2126x SHARC Processor Hardware Reference
bit is set. This indicates that a new word has just been
RXS
bit.
RXS
) is also available for polling. This bit may have
SPIF
is set at the same time as
SPIF
or .
CLKPL
bit is set, and consequently before new data has been
buffer. For
RXSPI
bit to be set (after
RXS
SPIBAUD
Serial Peripheral Interface Port
. The
RXSPI
. The latency is typically a
SPICLK
,
CPHASE
RXSPI
period after the last
SPICLK
bit is set. In general,
SPIF
SPIBAUD<4
= 2 or
SPIBAUD SPIBAUD
is set) before reading the
SPIF
settings (
SPIBAUD > 4
bit defines
TXS
bit is set
RXS
, and the baud
TIMOD
is full ( =
TIMOD
is set.
RXS
; for a master
RXS
edge,
SPICLK
is set
SPIF
). The bit is
SPIF
= 3, the proces-
), is set before
RXS
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