Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 126

Branches and Sequencing
In delayed branch,
branches
(DB)
is because the DSP executes the two instructions after the branch while
the pipeline fills with instructions from the new location. This is shown in
the sample code below.
call fft1024 (DB);
...
...
jump (pc,10) (DB);
As shown in Table 3-4
tions after the branch, while the instruction at the branch address is
fetched and decoded. In the case of a
address after the branch instruction. While delayed branches use the
instruction pipeline more efficiently than immediate branches, delayed
branch code can be harder to understand because of the instructions
between the branch instruction and the actual branch.
Table 3-4. Pipelined Execution Cycles for Delayed Branch
(JUMP or CALL)
Cycles
Execute
Decode
Fetch
N is the branching instruction, and J is the instruction branch address.
1. For a delayed branch call, N + 3 is pushed on PC stack, not N + 1
Table 3-5. Pipelined Execution Cycles for Delayed Branch (Return)
Cycles
Execute
Decode
Fetch
N is the branching instruction, and R is the instruction at the return address.
1. R (N + 3 pushed in figure...) popped from PC stack
3-14
and
JUMP CALL
modifier, no instruction cycles are lost in the pipeline. This
and Table
1 2
N N + 1
N + 1 N + 2
N + 2 1
J
1 2
1 N + 1
N
N + 1 N + 2
N + 2 R
ADSP-2126x SHARC Processor Hardware Reference
/ instructions that use the delayed
RETURN
3-5, the DSP executes the two instruc-
, the return address is the third
CALL
3
N + 2
J
J + 1
3
N + 2
R
R + 1
4
J
J + 1
J + 2
4
R
R + 1
R + 2