Table A-39. Group F Sources – Pin Output Enable (Cont'd)
Selection Code
011001 (0x19)
011010 (0x1A)
011011 (0x1B)
011100 (0x1C)
011101 (0x1D)
011110 (0x1E)
011111 (0x1F)
100000 (0x20)
100001 (0x21)
100010 (0x22)
100011 (0x23)
100100 (0x24)
100101 (0x25)
100110 (0x26)
100111 (0x27)
101000 (0x28)
101001 (0x29)
ADSP-2126x SHARC Processor Hardware Reference
Source Signal
SPORT4_FS_PBEN_O
SPORT4_DA_PBEN_O
SPORT4_DB_PBEN_O
SPORT5_CLK_PBEN_O
SPORT5_FS_PBEN_O
SPORT5_DA_PBEN_O
SPORT5_DB_PBEN_O
TIMER0_PBEN_O
TIMER1_PBEN_O
TIMER2_PBEN_O
FLAG10_PBEN_O
FLAG11_PBEN_O
FLAG12_PBEN_O
FLAG13_PBEN_O
FLAG14_PBEN_O
FLAG15_PBEN_O
Reserved
Registers Reference
Description
Select Serial Port 4 Frame Sync Output Enable
as the source
Select Serial Port 4 Data Channel A Output
Enable as the source
Select Serial Port 4 Data Channel B Output
Enable as the source
Select Serial Port 5 Clock as the Output
Enable source
Select Serial Port 5 Frame Sync Output Enable
as the source
Select Serial Port 5 Data Channel A Output
Enable as the source
Select Serial Port 5 Data Channel B Output
Enable as the source
Select Timer 0 Output Enable as the source
Select Timer 1 Output Enable as the source
Select Timer 2 Output Enable as the source
Select Flag 10 Output Enable as the source
Select Flag 11 Output Enable as the source
Select Flag 12 Output Enable as the source
Select Flag 13 Output Enable as the source
Select Flag 14 Output Enable as the source
Select Flag 15 Output Enable as the source
A-141
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