SPORT Programming Examples
To avoid hanging the processor core—check the buffer's full/empty status
when the core's program reads a word from a serial port's receive buffer or
writes a word to its transmit buffer. This condition can also happen to an
external device, for example a host processor, when it is reading or writing
a serial port buffer. The full/empty status can be read in the
register. Reading from an empty receive buffer or writing to a full
SPCTLx
transmit buffer causes the processor (or external device) to hang, while it
waits for the status to change.
To support debugging buffer transfers, the processor has a Buffer
Hang Disable (
cessor core from detecting a buffer-related stall condition,
permitting debugging of this type of stall condition. For more
information, see the
Multiple interrupts can occur if both SPORTs transmit or receive data in
the same cycle. Any interrupt can be masked in the
interrupt is later enabled in the
rupt latch bit in the
interrupt has occurred in the same time period.
When serial port data packing is enabled (
registers), the transmit and receive interrupts are generated for 32-bit
packed words, not for each 16-bit word.
SPORT Programming Examples
The third listing,
using DMA chaining and the internal loopback feature of the
SPORT0
serial port. In this example,
the two TCBs for each
continually send and receive data.
The second listing,
using DMA and the internal loopback feature of the serial port. In
SPORT4
9-74
) bit. When set (= 1), this bit prevents the pro-
BHD
bit discussion on
BHD
LIRPTL
or
IRPTL
LIRPTL
Listing
9-1, transmits a buffer of data from
drives the clock and frame sync, and
SPORT5
are set up to ping-pong back and forth to
SPORT
Listing
9-2, transmits a buffer of data from
ADSP-2126x SHARC Processor Hardware Reference
on page
IMASK
register, the corresponding inter-
registers must be cleared in case the
in the
PACK=1
bits of the
DXS
9-56.
register; if the
Control
SPCTLx
to
SPORT1
to
SPORT5
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