Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 301

field = 0x0000) until some event occurs that loads the
nonzero value. Writing all zeros to the address field of the chain pointer
register ( ) also disables chaining.
CP

Chained DMA operations may only occur within the same chan-
nel. The processor does not support cross-channel chaining.

The parallel port and IDP port do not support DMA chaining.
A d d r es s P oi n ter
t o N e xt T C B
Chaining is not available on the IDP or parallel ports.
An "x" denotes the DMA channel used.
Figure 7-1. TCB Chaining
The chain pointer register is 20 bits wide. The lower 19 bits are the mem-
ory address field. Like other I/O processor address registers, the chain
pointer register's value is offset to match the starting address of the proces-
sor's internal memory before it is used by the I/O processor. On the
ADSP-2126x, this offset value is 0x0008 0000.
Bit 19 of the chain pointer register is the Program Controlled Interrupts
( ) bit. This bit controls whether an interrupt is latched after each
PCI
DMA completes or whether the interrupt is latched after the entire DMA
sequence completes. If set, the
occur after every DMA in the chain. If cleared, an interrupt occurs at the
completion of the entire DMA sequence.
ADSP-2126x SHARC Processor Hardware Reference
C P SPx
C SPx
I M S P x
I IS Px
bit enables a DMA channel interrupt to
PCI
I/O Processor
register with a
CP
L o w e s t
Addre s s
Highe s t
Addre s s
7-11