Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 830

Index
MV (multiplier overflow) bit,
MVS bit, 2-27
MVS (multiplier floating-point overflow)
bit, A-19
Mx registers, 4-2, 4-16, A-37,
N
nearest, round-to, 2-13
negate breakpoint (NEGx) bit, A-49,
nested interrupt routines,
nested loops, 3-27
nesting multiple interrupts enable
(NESTM) bit, A-6
NESTM bit, 3-58
next descriptor (chain) pointer address bits,
A-107
no boot mode (NOBOOT) bit,
normal mode, 13-10
normal word, 5-13, 5-26
accesses with LW, G-8
data access, 5-26
data storage, 5-2
mixing 32-bit data and 48-bit
instructions, 5-13
SIMD mode, 5-44, 5-46
SISD mode, 5-40, 5-42
not, logical, 2-17
not-a-number (NAN),
not equal (NE), 3-19
O
one shot option, 13-11
OPD
pin, 10-8
open drain
drivers support, 1-12
mode (OPD), 10-8
operands, 2-13, 2-17, 2-23, 2-31, 2-38,
G-2
I-20
3-19
G-7
A-51
3-61
A-53
2-13
ADSP-2126x SHARC Processor Hardware Reference
operands and results
storage for, A-21
operation mode See OPMODE bit
OPMODE bit, 9-11, 9-15, 9-20, 9-27,
9-54, A-76
or, logical, 2-17
OSPIDENS bit, A-57
OSPIDENS (operating system process ID)
register enable bit,
OSPID (operating system process ID),
A-61
OSPID register enable See OSPIDENS bit
output pulse width, defined,
overflow See ALU, multiplier, or shifter
P
PACK bit, 9-54, A-76
PACKEN bit, A-94
packing (16-to-32 data),
packing enable
(SPI port) See PACKEN bit
packing modes, 8-1
mode 00, 11-10
mode 01, 11-10
mode 10, 11-9
mode 11, 11-9
packing modes in IDP_PP_CTL,
illustrated, 11-8
packing sequence, for 32-bit data,
packing unit, 11-8
parallel assembly code See multifunction
computation or SIMD operations
Parallel Data Acquisition Port Control
(IDP_PDAP_CTL) register,
parallel data acquisition port (PDAP), 8-5,
11-6, A-155
parallel data acquisition port (PDAP)
packing unit, 11-8
parallel input mode, 11-6
parallel operations, 2-41,
A-61
13-11
2-7
8-7
A-153
G-7