"reads" of memory that do not exist. Catastrophic events are treated as
high priority events. In comparison, normal interrupts are "determinis-
tic"—specific events emanating from a source (the causes), the result of
which is the generation of an interrupt. The expiration of a timer can gen-
erate an interrupt, a signal that a serial port has received data that must be
processed, a signal that an SPI has either transmitted or received data, and
other software interrupts like the insertion of a trap that causes a break-
point—all are conditions which identify to the core that an event has
occurred.
Since DAI-specific events generally occur infrequently, the DAI IC classi-
fies such interrupts as either high or low priority interrupts. Within these
broad categories, users can indicate which interrupts are high and which
are classified as low.
Any interrupt causes a two-cycle stall, since it forces the core to stop pro-
cessing an instruction in process, then vector to the Interrupt Service
routine (ISR), (which is basically an Interrupt Vector Table (IVT)
lookup), then proceed to implement the instruction referenced in the
IVT. For more information, see
Appendix B, Interrupt Vector
When an interrupt from the DAI must be serviced, one of the two core
ISRs must query the DAI's Interrupt Controller to determine the
source(s). Sources can be any one or more of the Interrupt Controller's
32-configurable channels (
"DAI Interrupt Controller Registers" on page A-167.
DAI events trigger two interrupts in the primary IVT—one each for low
or high priority. When any interrupt from the DAI needs to be serviced,
one of the two core ISRs must interrogate the DAI's Interrupt Controller
to determine the source(s).
Reading the DAI's interrupt latches clears them. Therefore, the
ISR must service all the interrupt sources it discovers.
ADSP-2126x SHARC Processor Hardware Reference
"Interrupt Vector Addresses" in
Addresses.
).
For more information, see
DAI_INT[31:0]
Digital Audio Interface
12-27
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