Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 662

Core Registers
pins when the
AD
set, the parallel port is not operational and the four dedicated
pins switch to their alternate state—

When the
shuts down the clock to the SPI), the
the
FLGS7–0
with the clock.

Programs cannot change the Output Selects of the
and provide a new value in the same instruction. Instead, programs
must use two write instructions—the first to change the output
select of a particular
value.
FLAGS (Bits 31-16)
FLG15O
FLAG15 Output Select
FLG15
FLAG15 Value
FLG14O
FLAG14 Output Select
FLG14
FLAG14 Value
FLG13O
FLAG13 Output Select
FLG13
FLAG13 Value
FLG12O
FLAG12 Output Select
FLG12
FLAG12 Value
-For all FLGx bits, FLAGx values are as follows: 0=low, 1=high.
-For all FLGxO bits, FLAGx output selects are as follows: 0=FLAGx Input, 1=FLAGx Output.
-U indicates the bit value is unknown at reset.
Figure A-11. FLAGS Register (Upper Bits)
A-40
bit in the
PPFLGS
bit (bit 30 in the
SPIPDN
register bits) because the
"Power Management Registers" on page
pin, and the second to provide the new
FLG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 U 0 U 0 U 0 U
ADSP-2126x SHARC Processor Hardware Reference
register (= 1). While this bit is
SYSCTL
, , , and
IRQ0 IRQ1 IRQ2
register) is set (= 1 which
PMCTL
pins cannot be used (via
FLGx
pins are synchronized
FLGx
0 U 0 U 0 U 0 U
FLAG[0:3]
.
TMREXP
A-65.
register
FLAGS
FLG8
FLAG8 Value
FLG8O
FLAG8 Output Select
FLG9
FLAG9 Value
FLG9O
FLAG9 Output Select
FLG10
FLAG10 Value
FLG10O
FLAG10 Output Select
FLG11
FLAG11 Value
FLG11O
FLAG11 Output Select