Spi Clock Signal (Spiclk) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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SPI Interface Signals

ports in a system that has multiple devices.

master-slave connections between two ADSP-2126x devices.

SPI-COMPATIBLE MASTER DEVICE

Figure 10-2. Master-Slave Interconnections

SPI Clock Signal (SPICLK)

signal is the Serial Peripheral Interface Clock signal. This con-

trol signal is driven by the master and regulates the flow of data bits. The

master may transmit data at a variety of baud rates. The

once for each bit transmitted.

signal is a gated clock that is only active during data transfers,

and only for the duration of the transferred word. The number of active

edges is equal to the number of bits driven on the data lines. The clock

rate can be as high as one-fourth the core clock rate. For master devices,

the clock rate is determined by the 15-bit value of the Baud Rate register

For more information, see "SPI Baud Setup Register (SPI-

BAUD)" on page 10-34.

signal; when the SPI is a slave,

ignore the serial clock if the slave-select input is deasserted (

For slave devices, the value in the

ADSP-2126x SHARC Processor Hardware Reference

SPI-COMPATIBLE SLAVE DEVICE

is an input signal. Slave devices

is an output

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