Spi Transmit Data Buffer Register (Txspi) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Registers

SPI Transmit Data Buffer Register (TXSPI)

The Transmit Data Buffer register (
register. Data is loaded into this register before being transmitted. Just
prior to the beginning of a data transfer, the data in
the Transmit Shift Data (
be done at any time and does not interfere with, or initiate, SPI transfers.
With DMA enabled for transmit operations, the IOP loads data into this
register. Core writes to
the DMA data to be transmitted.
With DMA enabled for receive operations, the contents of the
ter are repeatedly transmitted. A normal core write to
in this mode, and this data is transmitted. If the Send Zeroes Control bit
( ) is set,
SENDZ TXSPI
If multiple writes to
only the last data written is transmitted. None of the intermediate values
written to
TXSPI
not recommended. To avoid overwriting data, be sure to poll the
before writing to

To prevent transmit collision errors, ensure that the program writes
to the
TXSPI
writing to
from writing to
exist in
device select) occurs.
The
TXCOL
are attempts to write to the
set and the program wants to send new data. To ensure that
is written into before the next load to a Shift register occurs, write
to the
TXSPI
register) goes from one to zero.
10-38
) register. A normal core read of
SFDR
should not be made to prevent corrupting
TXSPI
resets once the data is transferred from
occur while a transfer is already in progress,
TXSPI
are transmitted. Multiple writes to
.
TXSPI
register before the load to the Shift register occurs by
whenever
TXSPI
when
TXSPI
before the first SPI clock edge (or negative edge of
TXSPI
bit can be set when there is a
register as soon as the
ADSP-2126x SHARC Processor Hardware Reference
) is a 32-bit read-write (RW)
TXSPI
TXSPI
is cleared. Programs should refrain
TXS
is set. For slave mode, data should
TXS
TUNF
register. In this case,
TXSPI
bit (bit 0 in the
SPIF
is loaded into
TXSPI
can
TXSPI
regis-
TXSPI
is permitted
TXSPI
to .
TX TXSR
are possible but
bit
TXS
condition and there
is not
TXS
TXSPI
SPISTAT