Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 127

Besides being more challenging to code, delayed branches impose some
limitations that stem from the instruction pipeline architecture. Because
the delayed branch instruction and the two instructions that follow it
must execute sequentially, the instructions in the two locations that follow
a delayed branch instruction cannot be:
• Other branches (no
Normally, it is not valid to have two conditional instructions that
use the (
tion of those instructions is mutually exclusive, it is allowed. For
example:
if gt jump (PC, 7) (db)
if le jump (PC,11) (db)
• Any stack manipulations (no
the stack or
PC
• Any loops or other breaks in sequential operation (no
instructions)
IDLE

Development software for the DSP should always flag these types
of instructions as code errors in the two locations after a delayed
branch instruction.
Delayed branches and the instruction pipeline also influence interrupt
processing. Because the delayed branch instruction and the two instruc-
tions that follow it always execute sequentially, the DSP does not
immediately process an interrupt that occurs in between a delayed branch
instruction and either of the two instructions that follow. Any interrupt
that occurs during these instructions is latched, but is not processed until
the branch is complete.
This may be useful when two instructions must execute atomically (with-
out interruption), such as when working with semaphores. In the
ADSP-2126x SHARC Processor Hardware Reference
,
JUMP CALL
) option follow each other. However, where the execu-
DB
stack pointer register)
PC
Program Sequencer
, or instructions)
RETURN
or instructions or writes to
PUSH POP
or
DO/UNTIL
3-15