Timer Status Registers (Tmxstat) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Timer Status Registers (TMxSTAT)

The global status registers
are sticky and require a write-one to clear operation. During a status regis-
ter read access, all reserved or unused bits return a zero. Each timer
generates a unique processor interrupt request signal,
A common status register latches these interrupts. Interrupt bits are sticky
and must be cleared to assure that the interrupt is not reissued.
Each timer is provided with its own sticky status register
enable or disable an individual timer, the
example, writing a one to bit 8 sets the
clears it. Writing a one to both bit 8 and bit 9 clears
status register returns the
remaining
TIMxEN
15 14 13 12 11 10
TIM2DIS (W1C)
Timer 2 Disable
TIM2EN
Timer 2 Enable
TIM1DIS (W1C)
Timer 1 Disable
TIM1EN
Timer 1 Enable
TIM0DIS (W1C)
Timer 0 Disable
TIM0EN
Timer 0 Enable
TIM2OVF
Timer 1 Counter Overflow Error
Figure A-69. TMxSTAT Register
ADSP-2126x SHARC Processor Hardware Reference
are shown in
TMxSTAT
state on both bit 8 and bit 9. The
TIM0EN
bits operate similarly.
9 8 7 6
Registers Reference
Figure A-69. Status bits
TIMxIRQ
bit is set or cleared. For
TIMxEN
bit; writing a one to bit 9
TIM0EN
TIM0EN
5 4 3 2 1 0
TIM0IRQ (W1C)
Timer 0 Interrupt
TIM1IRQ (W1C)
Timer 1 Interrupt
TIM2IRQ (W1C)
Timer 2 Interrupt
TIM0OVF
Timer 0 Counter
Overflow Error
TIM1OVF
Timer 1 Counter
Overflow Error
.
bit. To
TIMxEN
. Reading the
A-159