Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 90

Barrel Shifter (Shifter)
Some shifter operations produce 8-bit or 6-bit results. As shown in
Figure 2-10, the shifter places these results in either the shf8 field or the
bit6 field and sign-extends the results to 32 bits. The shifter always returns
a 32-bit result.
39
39
Figure 2-10. Register File Fields for Shifter Instructions
The shifter supports bit field deposit and bit field extract instructions for
manipulating groups of bits within an input. The Y input for bit field
instructions specifies two 6-bit values: bit6 and len6, which are positioned
in the register as shown in
Ry
len6 as positive integers. Bit6 is the starting bit position for the deposit or
extract, and len6 is the bit field length, which specifies how many bits are
deposited or extracted.
39
Figure 2-11. Register File Fields for FDEP, FEXT Instructions
Field deposit (
ter (starting at the LSB of the 32-bit integer field) and deposit the bits as
directed anywhere within the result register. The bit6 value specifies the
starting bit position for the deposit.
bit6 and len6, work in a field deposit instruction:
2-32
32-BIT Y INPUT OR RESULT
8-BIT Y INPUT OR RESULT
Figure
19
LEN6
12-BIT Y INPUT
) instructions take a group of bits from the input regis-
Fdep
ADSP-2126x SHARC Processor Hardware Reference
15
SHF8
2-10. The shifter interprets bit6 and
13
BIT6
Figure 2-11 shows how the inputs,
7 0
7 0
7
0