Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 162

Interrupts and Sequencing
Except for reset, all interrupt service routines should end with a
return-from-interrupt (
so there is no return address. The last instruction of the reset service rou-
tine should be a
If programs force an interrupt by writing to a bit in the
processor recognizes the interrupt in the following cycle, and two cycles of
branching to the interrupt vector follow the recognition cycle.
The DSP responds to interrupts in three stages: synchronization and
latching (1 cycle), recognition (1 cycle), and branching to the interrupt
vector (2 cycles).
lined execution cycles for interrupt processing.
Table 3-21. Pipelined Execution Cycles for Interrupt During Single Cycle
Instruction
Cycles 1
Execute 1
N – 1
Decode N
Fetch N + 1
N is the loop start instruction and N + 3 is the instruction after the loop.
1. Interrupt occurs
2. Interrupt recognized
3. N + 1 pushed on PC stack; N + 1 suppressed
4. Interrupt Vector output
5. N + 2 suppressed
3-50
) instruction. After reset, the PC stack is empty,
RTI
to the start of the program.
JUMP
Table 3-21, Table
2 3
N NOP
N + 1 –> N + 2 –>
3
NOP NOP
2 4
N + 2 V
ADSP-2126x SHARC Processor Hardware Reference
3-22, and Table 3-22
4
NOP
V
5
V + 1
register, the
IRPTL
show the pipe-
5
V
V + 1
V + 2