Instruction Register - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

JTAG Related Registers

Instruction Register

The Instruction register shifts an instruction into the processor. This
instruction selects the performed test and/or the access of the test data reg-
ister. The instruction register is 5 bits long with no parity bit. A value of
10000 binary is loaded (LSB nearest
whenever the TAP reset state is entered.
The new JTAG instruction set, shown in
for each instruction. Bit 0 is nearest
registers are placed into test modes by any of the public instructions. The
instructions affect the DSP as defined in the 1149.1 specification. The
optional instructions
the processor.
Table 6-2. JTAG Instruction Register Codes
43210 Register
11111 Bypass
00000 Boundary
10000 Boundary
11000 Boundary
11100 BRKSTAT
01001 EEMUIN
01011 EEMUOUT
11101 EMUPID
The entry under "Register" is the serial scan path, either Boundary or
Bypass in this case, enabled by the instruction.
ister paths. The 1-bit Bypass register is fully defined in the 1149.1
specification.
6-6
TDO
TDO
, , and
RUNBIST IDCODE
Instruction
BYPASS
EXTEST
SAMPLE
INTEST
EMULATION
EMULATION
EMULATION
REV-id register
ADSP-2126x SHARC Processor Hardware Reference
) into the Instruction register
Table 6-2, lists the binary code
and bit 4 is nearest
are not supported by
USERCODE
Inmode
0
0
0
1
0
0
0
0
Figure 6-1 shows these reg-
. No data
TDI
Outmode
0
1
0
1
0
0
0
0